1.1 Related Art
When programmable units (FPGAs, DPGAs, DFPs (according to German Patent 44 16 881 A1)), summarized below as "units" for the sake of simplicity, are combined into a cluster, there are two methods of performing the programming. A cluster is a multi-dimensional interconnected array of units or groups of units.
For each unit there is a primary logic unit (PLU) with the help of which the unit is programmed. In other words, a PLU addresses a unit of the cluster. This PLU may be designed as an EPROM or as a computer system. The data can be transmitted to the unit in a serial or parallel form. In parallel data transmission, the data in the unit is converted to a serial bit stream which configures the unit. PA1 Only one PLU is available for all units of the cluster. The individual units are daisy-chained. Programming is accomplished by a serial bit stream. The PLU addresses only the first unit and the data is sent through a serial line to the units of the cluster. The data is passed as a bit stream through all the units of the cluster and thus configures their programmable elements. Here again, the configuration data can be transmitted in serial or parallel form. The PLU can again be embodied as an EPROM or as a computer system. PA1 When using a computer system, there is the possibility of using the address lines for a chip select to address and configure individual units separately. PA1 Due to the method of addressing, the actual arrangement of units is not represented. PA1 It is impossible to address a single element of any unit in the cluster to perform reconfiguration. Only a complete unit can be addressed, and it must be reconfigured as a whole. PA1 Due to the fixed assignment of addresses to the individual processors of a parallel computer, there is a static assignment of addresses. In addition, a large amount of resources are needed in allocating addresses for the individual processors.
With a parallel computer, a fixed address by means of which addressing is performed is assigned to each of its processors.
1.2 Problems
The previous methods of addressing a unit have a number of problems and weaknesses.
1.3 Improvement Through the Invention
Individual configurable elements of a unit can be addressed with the help of this invention. It is thus possible to address the individual elements directly for reconfiguration. This is a prerequisite for being able to reconfigure parts of the unit by an external PLU without having to change the entire configuration of the unit. In addition, the addresses for the individual elements of the units are automatically generated in the X and Y directions, so that the actual arrangement of units and configurable elements is represented. Manual allocation of addresses is not necessary due to automatic address generation.
The patent claims concern details and special embodiments as well as features of address generation according to this invention.